In this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.
TCAD simulation is done for a high voltage RF SIT. Pinch voltage (V_Pinch, as defined by the gate voltage required to turn the device off for a certain applied drain voltage) may be affected by the interface charges. Generally speaking, the V_Pinch is very sensitive to the channel doping concentration.
If the oxide / SiC interface charges are positive charges, the V_Pinch is higher. Please notice the gain is also reduced – this may affect the AC performance.
The depletion width is derived from converting the measured Schottky Diode high frequency CV to Depletion Width vs. Voltage. The 1/C2 vs. V plot may also be used to extract the gate metal work function.
SIT gate metal workfunction is extracted to be 5.42V.
SIT channel doping profile is generated by converting the high voltage HF Schottky Diode CV to 1/C2 vs. V plot. When the frequency varies from 100 KHz to 1MHz, there is a small shift of the extracted doping profile. The difference between the measured doping concentrations at these voltages may be caused by the deep level traps in the 4H SiC epitaxial layer. When the test frequency is lower than 100 KHz, there is no significant shift. The SIT channel doping profile is extracted from the HF Schottky Diode CV. The deep level trap density is the difference between the two doping profiles.
The Surface Potential at the thermal oxide / 4H SiC interface vs. gate voltage is derived by the integration technique for the measured HF MOS CV.
Oxide / Silicon or 4H SiC interface trap density may be extracted by comparing the measured high-frequency MOS CV and a theoretical, defect-free high frequency MOS CV:
Dit (eV-1×cm-2) = 1/q ×Cox × d(Delta_VG)/ dØS (1)
Where q is the electron charge, Cox is the oxide capacitance, Dit is the oxide interface defect density, Delta_VG is the gate voltage difference between measured and theoretical HF MOS CVs, corresponding to the same capacitance in the CV plot, and ØS is the surface potential at the SiC / oxide interface. Surface Potential vs. Delta_VG and Interface Trap Density vs. Surface Potential plots are presented in this paper.
Oxide / Si or 4H SiC interface trap density, deep level trap density, device channel doping profile, gate metal workfunction are characterized with high voltage (100V), high frequency (up to 1MHz) MOS and Schottky Diode CV techniques. TCAD simulation shows the effects of these defects on DC and AC performance. The deep level trap density of 4H SiC (average) = 1×1015 cm-3 about 1 order of magnitude higher than lightly doped silicon (= 1×1014 cm-3). The interface state density of 4H SiC is (average) = 4×1011 cm-2 eV-1, also about 10 times higher than silicon.
5:00 PM–7:00 PM Apr 23, 2019 (US - Arizona)
PCC North, 300 Level, Exhibit Hall C-E