Date/Time: 04-23-2019 - Tuesday - 05:00 PM - 07:00 PM
Robin Daugherty1 Dragica Vasileska1

1, Arizona State University, Tempe, Arizona, United States

This simulation work explores the thermal effects on electrical characteristics of CMOS devices and circuits using a multiscale dual-carrier approach. Simulating for electron and hole transport simultaneously allows for complementary logic gates to be simulated at the device level, while current and voltage continuity are maintained at the circuit level. Further, the electrical model couples with a multiscale thermal solver, which solves for electron-phonon and hole-phonon interactions at the device level and phonon-phonon thermal transport in the packaging level. This methodology allows for the study of package level thermal transport without sacrificing the nuances of device self-heating, ultimately providing a more comprehensive understanding of how these interactions affect power consumption in CMOS systems.

The electrical model is comprised of an ensemble Monte Carlo simulator coupled with a Poisson solver. This framework provides accurate electrical characteristics in quasi-static regimes by iteratively solving for the potential profile and the electric fields then simulating the effect of the electric field on charge carriers. The Monte Carlo simulator solves the Boltzmann Transport by balancing each particle’s movement in real and momentum space with the collision integral through probabilistic scattering mechanisms. This framework provides current and voltage characteristics for each device; current and voltage continuity are maintained by solving at the circuit level.

Similarly, the methodology for simulating thermal characteristics includes two scales. At the device scale, the energy balance equation determines the transfer of energy from charge carriers to phonons. High-energy electrons or holes relinquish energy to optical and acoustic phonons through scattering and optical phonons decay into acoustic phonons. At the package level, a Fourier law solver simulates the subsequent conduction of heat in the form of lattice vibrations.

This framework proved effective in previous simulations for the electro-thermal characteristics in NMOS devices. This work demonstrates the effectiveness of the dual-carrier electrical solver in simulating CMOS circuits. Future work requires the coupling the dual-carrier electrical solver with the previously proven thermal solver to provide comprehensive electro-thermal simulations of CMOS systems.

Meeting Program

Symposium Sessions

5:00 PM–7:00 PM Apr 23, 2019 (US - Arizona)

PCC North, 300 Level, Exhibit Hall C-E